06187678 is referenced by 188 patents and cites 30 patents.

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.

Title
High density integrated circuit packaging with chip stacking and via interconnections
Application Number
9/379716
Publication Number
6187678 (B1)
Application Date
August 24, 1999
Publication Date
February 13, 2001
Inventor
Jerzy Maria Zalesinski
Essex Junction
VT, US
Charles Gerard Woychik
Vestal
NY, US
Viswanadham Puligandla
Lewisville
TX, US
Alan James Emerick
Warren Center
PA, US
Michael Anthony Gaynes
Vestal
NY, US
Agent
McGuireWoods
US
Agent
Ronald A Kaschak
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/44
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