06185644 is referenced by 122 patents and cites 56 patents.

A memory system having a master device and a plurality of memory subsystems, including first and second memory subsystems coupled to a first bus. Each memory subsystem includes a plurality of memory devices. The master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem. The first and second memory subsystems each include a transceiver device, a bus, and first and second memory devices. Each transceiver device connects to the first bus. The bus of each memory subsystem connects to each respective transceiver device, wherein each transceiver device is coupled between the first bus and each respective memory subsystem bus. The first and second memory devices in each memory subsystem are coupled respective transceiver devices via respective buses.

Title
Memory system including a plurality of memory devices and a transceiver device
Application Number
9/487524
Publication Number
6185644 (B2)
Application Date
January 19, 2000
Publication Date
February 6, 2001
Inventor
Mark Horowitz
Palo Alto
CA, US
Michael Farmwald
Berkeley
CA, US
Agent
Neil A Steinberg
US
Assignee
Rambus
CA, US
IPC
G06F 13/00
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