06184111 is referenced by 111 patents and cites 22 patents.

A process for forming a novel substrate material. The process includes providing a substrate, e.g., silicon wafer. The substrate has a stressed layer at a selected depth underneath a surface of the substrate. The stressed layer is at the selected depth to define a substrate material to be removed above the selected depth. The stressed layer comprises a deposited layer and an implanted region. The substrate also comprises a device layer overlying the stressed layer. The process includes forming a plurality of integrated circuit devices on the substrate material. A thermal treatment process at a temperature greater than about 400 degrees Celsius is included in the process of forming the integrated circuit devices. Next, the process includes providing energy to a selected region of the substrate to initiate a controlled cleaving action at the selected depth in the substrate, whereupon the cleaving action is made using a propagating cleave front to free a portion of the material to be removed from the substrate.

Title
Pre-semiconductor process implant and post-process film separation
Application Number
9/371589
Publication Number
6184111 (B2)
Application Date
August 10, 1999
Publication Date
February 6, 2001
Inventor
Nathan W Cheung
Albany
CA, US
Francois J Henley
Los Gatos
CA, US
Agent
Townsend and Townsend and Crew
US
Assignee
Silicon Genesis Corporation
CA, US
IPC
H01L 21/425
View Original Source