06167508 is referenced by 15 patents and cites 3 patents.

Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter. Addition speed increase may be achieved by dividing the register scoreboard logic into odd and even register scoreboard arrays on either side of the arbiter.

Title
Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency
Application Number
9/88818
Publication Number
6167508
Application Date
June 2, 1998
Publication Date
December 26, 2000
Inventor
Bruce A Gieseke
San Jose
CA, US
James A Farrell
Harvard
MA, US
Agent
Hamilton Brook Smith & Reynolds P C
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 9/38
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