06163048 is referenced by 211 patents and cites 4 patents.

A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Title
Semiconductor non-volatile memory device having a NAND cell structure
Application Number
9/51700
Publication Number
6163048
Application Date
April 16, 1998
Publication Date
December 19, 2000
Inventor
Loren T Lancaster
Colorado Springs
CO, US
Ryan T Hirose
Colorado Springs
CO, US
Agent
Bradley T Sako
Assignee
Cypress Semiconductor Corporation
CA, US
IPC
G11C 16/04
H01L 29/788
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