A modular Fibre Channel switch includes a data switching path and a message switching path to provide logical point to point connections between switch ports. The data switching path includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports. The switch includes a motherboard containing an embedded G.sub.-- Port ASIC, a message crossbar switch to handle message passing and shared memory that is used to perform data switching. The switch also includes a central processing unit daughter board and external switch port daughter boards.