06134573 is referenced by 6 patents and cites 8 patents.

An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.

Title
Apparatus and method for absolute floating point register addressing
Application Number
9/63282
Publication Number
6134573
Application Date
April 20, 1998
Publication Date
October 17, 2000
Inventor
Terry Parks
Austin
TX, US
Albert J Loper Jr
Cedar Park
TX, US
G Glenn Henry
Austin
TX, US
Agent
James W Huffman
Richard K Huffman
Assignee
IP First L L C
CA, US
IPC
G06F 9/30
View Original Source