06118724 is referenced by 78 patents and cites 180 patents.

An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.

Title
Memory controller architecture
Application Number
9/25726
Publication Number
6118724
Application Date
February 18, 1998
Publication Date
September 12, 2000
Inventor
Raymond Paul Higginbottom
New South Wales
AU
Agent
Fitzpatrick Cella Harper & Scinto
Assignee
Canon Information Systems Research Australia
JP
Canon Kabushiki Kaisha
JP
IPC
G11C 8/00
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