06117720 is referenced by 411 patents and cites 38 patents.

A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.

Title
Method of making an integrated circuit electrode having a reduced contact area
Application Number
486635
Publication Number
6117720
Application Date
April 28, 1997
Publication Date
September 12, 2000
Inventor
Steven T Harshfield
Emmett
ID, US
Agent
Fletcher Yoder & Van Someren
Assignee
Micron Technology
ID, US
IPC
H01L 9/00
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