06117181 is referenced by 87 patents and cites 6 patents.

The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit simulations which collective simulate a circuit is represented and controlled by a respective local synchronization thread ("LST") of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation. Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism. The barrier mechanism is used to ensure that all tests which are to request reservations of devices of the circuit simulation have requested from the hub such reservations before any test proceeds. In this way, the hub can establish the order in which such requests are granted in a repeatable manner. As each test enters the barrier mechanism, execution of the test is suspended and a reference to the test is added to a thread list. When all tests which are to enter the barrier have done so, each thread identified by a reference on the thread list is awakened and execution of the test resumes.

Title
Synchronization mechanism for distributed hardware simulation
Application Number
621816
Publication Number
6117181
Application Date
December 23, 1998
Publication Date
September 12, 2000
Inventor
Paul M Whittemore
Marlborough
MA, US
Glenn A Dearth
Groton
MA, US
Agent
Conley Rose & Tayon PC
Agent
B Noel Kivlin
Assignee
Sun Microsystems
CA, US
IPC
G06F 9/455
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