06114725 is referenced by 66 patents and cites 12 patents.

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

Title
Structure for folded architecture pillar memory cell
Application Number
787418
Publication Number
6114725
Application Date
June 9, 1998
Publication Date
September 5, 2000
Inventor
Jeffrey J Welser
Stamford
CT, US
Paul A Rabidoux
Winooski
VT, US
Jack A Mandelman
Stormville
NY, US
Howard L Kalter
Colchester
VT, US
David V Horak
Essex Junction
VT, US
Steven J Holmes
Milton
VT, US
Mark C Hakey
Milton
VT, US
Toshiharu Furukawa
Essex Junction
VT, US
Agent
Scully Scott Murphy & Presser
Agent
Eugene I Shkurko Esq
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 31/119
H01L 31/113
H01L 31/62
H01L 29/94
H01L 29/76
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