06112016 is referenced by 65 patents and cites 11 patents.

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.

Title
Method and apparatus for sharing a signal line between agents
Application Number
420494
Publication Number
6112016
Application Date
March 27, 1997
Publication Date
August 29, 2000
Inventor
William S F Wu
Cupertino
CA, US
Nicholas D Wade
Vancouver
WA, US
Norman J Rasmussen
Hillsboro
OR, US
Peter D MacWilliams
Aloha
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 13/00
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