06101143 is referenced by 8 patents and cites 6 patents.

A circuit and method for FPGAs to allow a user to supply a shutdown signal at an external pin which causes internal circuitry in the FPGA to turn off pass transistors in the word lines of every SRAM cell in the FPGA thereby preventing wasted power by current drain to ground through an SRAM cell that happens to be addressed when the FPGA is not being used.

Title
SRAM shutdown circuit for FPGA to conserve power when FPGA is not in use
Application Number
9/221225
Publication Number
6101143
Application Date
December 23, 1998
Publication Date
August 8, 2000
Inventor
Atul V Ghia
San Jose
CA, US
Agent
Ronald Craig Fish
Assignee
Xilinx
CA, US
IPC
G11C 7/00
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