06096598 is referenced by 136 patents and cites 13 patents.

The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form source/drain and bitline diffusion structures for use in pillar memory cells. Additionally, in another embodiment, the present invention is used to form source/drain and plate diffusion structures in pillar memory cells. Both preferred embodiments deposit conformal photoresist on a pillar structure and use an off-axis exposure process to recess a dopant source layer to the proper depth along the pillar. The recessed dopant source layer can then be used to form the source/drain/bitlines diffusions or source/drain/plate diffusions in the pillar memory device.

Title
Method for forming pillar memory cells and device formed thereby
Application Number
9/182388
Publication Number
6096598
Application Date
October 29, 1998
Publication Date
August 1, 2000
Inventor
Paul A Rabidoux
Winooski
VT, US
David V Horak
Essex Junction
VT, US
Steven J Holmes
Milton
VT, US
Mark C Hakey
Milton
VT, US
Toshiharu Furukawa
Essex Junction
VT, US
Agent
Schmeiser Olsen & Watts
Agent
Eugene I Shkurko
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/8242
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