06093945 is referenced by 44 patents and cites 7 patents.

A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer. The split-gate flash memory is formed by (a) forming a first dielectric layer having a trench region on a substrate; (b) forming a tunnel oxide layer in the trench region; (c) forming a first polysilicon layer covering the first dielectric layer and the tunnel oxide layer; (d) applying an anisotropic etching technique on the first polysilicon layer to form a pair of opposing polysilicon sidewall spacers on the sidewalls which will eventually become floating gates; (e) depositing an inter-poly dielectric layer on the polysilicon sidewall spacers and the tunnel oxide layer; (f) filling the channel area between the pair of polysilicon sidewall spacers with a second polysilicon layer; (g) planarizing the second polysilicon layer so that relative to the first dielectric layer to form a control gate; (h) removing the first dielectric layer, capping the control gate and the floating gate with a final oxide layer, and forming source and drain regions in the substrate using ion implantation. The split-gate flash memory eliminates the over-erase problem experienced with the self-aligned ETOX flash memory cells, while allowing its cell dimension to maintain at least the same using the conventional photolithography technique.

Title
Split gate flash memory with minimum over-erase problem
Application Number
9/113032
Publication Number
6093945
Application Date
July 9, 1998
Publication Date
July 25, 2000
Inventor
Yu Hao Yang
Hsinchu
TW
Agent
W Wayne Liauh
Assignee
Windbond Electronics
TW
IPC
H01L 29/788
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