06087202 is referenced by 48 patents and cites 17 patents.

A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips. The process consists, in a second step, in placing this assembly (111) in a mold (112) and in injecting an encasement material (106) into the mold so as to obtain, in a single molding operation, a parallelepipedal block (117) and then, in a subsequent step, in cutting the said parallelepipedal block (117) through its thickness into units, each constituting a semiconductor package.

Title
Process for manufacturing semiconductor packages comprising an integrated circuit
Application Number
9/90009
Publication Number
6087202
Application Date
June 3, 1998
Publication Date
July 11, 2000
Inventor
Andrea Cigada
Milan
IT
Laurent Herard
Bizonnes
FR
Juan Exposito
St. Nazaire les Eymes
FR
Agent
Theodore E Fleit Kain Gibbons Gutman & Bongini PL Galanthay
Assignee
STMicroelectronics
FR
IPC
H01L 21/44
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