06084429 is referenced by 253 patents and cites 11 patents.

A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.

Title
PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
Application Number
9/66076
Publication Number
6084429
Application Date
April 24, 1998
Publication Date
July 4, 2000
Inventor
Stephen M Trimberger
San Jose
CA, US
Agent
Jeanette S Harms
Adam H Tachner
Assignee
Xilinx
CA, US
IPC
H03K 19/177
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