06081887 is referenced by 28 patents and cites 4 patents.

A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stored predictor is accessible in one instruction cycle, and therefore provides minimum predictor latency. Update latency is minimized by storing multiple predictions in the front end stored predictor which are indexed by an index counter. The multiple predictions, as provided by the back end, are indexed by the index counter to select a particular one as current prediction on a given instruction pipeline cycle. The front end stored predictor also passes along to the back end predictor, such as through the instruction pipeline, a position value used to generate the predictions. This further structure accommodates ghost branch instructions that turn out to be flushed out of the pipeline when it must be backed up. As a result, the front end always provides an accurate prediction with minimum update latency.

Title
System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction
Application Number
78113
Publication Number
6081887
Application Date
November 12, 1998
Publication Date
June 27, 2000
Inventor
Joel S Emer
Acton
MA, US
Edward J McLellan
Holliston
MA, US
Simon C Steely Jr
Hudson
NH, US
Agent
Hamilton Brook Smith & Reynolds P C
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 9/32
View Original Source