06076175 is referenced by 34 patents and cites 7 patents.

A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of the chip reduces the amount of time required to test the chip to determine the acceptability of the chip and its actual bit error rate.

Title
Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits
Application Number
8/828505
Publication Number
6076175
Application Date
March 31, 1997
Publication Date
June 13, 2000
Inventor
Robert J Bosnyak
San Jose
CA, US
Robert J Drost
Palo Alto
CA, US
Agent
Finnegan Henderson Farabow Garrett & Dunner L
Assignee
Sun Microsystems
CA, US
IPC
G06F 11/00
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