06075730 is referenced by 134 patents and cites 6 patents.

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

Title
High performance cost optimized memory with delayed memory writes
Application Number
9/169729
Publication Number
6075730
Application Date
October 9, 1998
Publication Date
June 13, 2000
Inventor
Peter D MacWilliams
Aloha
OR, US
Andrew V Anderson
Portland
OR, US
Thomas J Holman
Portland
OR, US
David Nguyen
San Jose
CA, US
James A Gasbarro
Mountain View
CA, US
Abhijit M Abhyankar
Sunnyvale
CA, US
Paul G Davis
San Jose
CA, US
Craig E Hampel
San Jose
CA, US
Donald C Stark
Los Altos
CA, US
Frederick A Ware
Los Altos Hills
CA, US
Richard M Barth
Palo Alto
CA, US
Agent
Pennie & Edmonds
Assignee
Intel Corporation
CA, US
Rambus Incorporated
CA, US
IPC
G11C 7/00
View Original Source