06073230 is referenced by 51 patents and cites 39 patents.

An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a first group of contiguous instruction bytes within the instruction cache, as well as a corresponding branch prediction block. The branch prediction block is stored in a branch prediction storage, and includes a predicted sequential way value. The control unit is further configured to convey a second index and a second way to the instruction cache in a second clock cycle succeeding the first clock cycle. This second index and second way select a second group of contiguous instruction bytes from the instruction cache. The second way is selected to be the predicted sequential way value stored in the branch prediction block corresponding to the first group of contiguous instruction bytes in response to a branch prediction algorithm employed by the control unit predicting a sequential execution path. Advantageously, a set associative instruction cache utilizing this method of way prediction may operate at higher frequencies (i.e., lower clock cycles) than if tag comparison were used to select the correct way.

Title
Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
Application Number
8/873113
Publication Number
6073230
Application Date
June 11, 1997
Publication Date
June 6, 2000
Inventor
Thang M Tran
Austin
TX, US
James K Pickett
Austin
TX, US
Agent
Conley Rose & Tayon
Agent
Lawrence J Merkel
B Noel Kivlin
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 9/38
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