06072236 is referenced by 248 patents and cites 12 patents.

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Title
Micromachined chip scale package
Application Number
8/612059
Publication Number
6072236
Application Date
March 7, 1996
Publication Date
June 6, 2000
Inventor
Warren M Farnworth
Nampa
ID, US
David R Hembree
Boise
ID, US
Salman Akram
Boise
ID, US
Agent
Task Britt & Rossa
Assignee
Micron Technology
ID, US
IPC
H01L 23/52
H01L 23/48
H01L 29/40
H01L 23/04
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