06070217 is referenced by 115 patents and cites 25 patents.

Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise. The RAM is Fast Page Mode (FPM) and Extended Data Output (EDO) or Synchronous DRAM (SDRAM).

Title
High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance
Application Number
676609
Publication Number
6070217
Application Date
May 12, 1998
Publication Date
May 30, 2000
Inventor
Mark W Kellogg
Essex Juntion
VT, US
Bruce G Hazelzet
Essex Juntion
VT, US
Brian J Connolly
Williston
VT, US
Agent
Whitman Curtis & Whitham
Agent
Robert A Walsh Esq
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 12/06
G06F 12/00
G06F 13/40
G06F 13/00
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