06061781 is referenced by 14 patents and cites 2 patents.

An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Title
Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide
Application Number
9/108945
Publication Number
6061781
Application Date
July 1, 1998
Publication Date
May 9, 2000
Inventor
Arturo Martin de Nicolas
Austin
TX, US
Albert J Loper Jr
Cedar Park
TX, US
Dinesh K Jain
Austin
TX, US
Agent
James W Huffman
Richard K Huffman
Assignee
IP First
CA, US
IPC
G06F 7/52
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