06051881 is referenced by 13 patents and cites 7 patents.

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

Title
Forming local interconnects in integrated circuits
Application Number
8/986097
Publication Number
6051881
Application Date
December 5, 1997
Publication Date
April 18, 2000
Inventor
Stephen C Horne
Austin
TX, US
John C Holst
San Jose
CA, US
Raymond T Lee
Sunnyvale
CA, US
Christopher A Spence
Sunnyvale
CA, US
Craig S Sander
Mountain View
CA, US
Nicholas J Kepler
San Jose
CA, US
Asim A Selcuk
Cupertino
CA, US
Richard K Klein
Mountain View
CA, US
Agent
Foley & Lardner
Assignee
Advanced Micro Devices
CA, US
IPC
H01L 29/40
H01L 23/52
H01L 23/48
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