06051468 is referenced by 46 patents and cites 6 patents.

A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) structure is fabricated by first forming a plurality of trenches in a semiconductor substrate which includes a major surface. The trenches are then lined with insulating material and thereafter filled with conductive material. The process of filling the conductive material in the trenches normally involves an over-etching step for preventing any residual material remaining on the major surface. The over-etching of the conductive material in the trenches alters the evenness of the major surface and presents a problem for the later angular ion implantation of the source layer. As a consequence, the source layer formed includes asymmetrical source segments which generates nonuniform threshold voltage and punch-through tolerance in the MOSFET structure. The inventive method provides a spacer layer to compensate for the unevenness of the major surface. Prior to the ion implantation of the source layer, the spacer layer is formed above the conductive material and surrounding the insulating material adjacent the major surface. Source segments thus formed are symmetrical in shape enabling the fabricated MOSFET structure to operate with uniform punch-through tolerance, uniform threshold voltage, and uniform current distribution during normal operation.

Title
Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance
Application Number
8/929751
Publication Number
6051468
Application Date
September 15, 1997
Publication Date
April 18, 2000
Inventor
Fwu Iuan Hshieh
Saratoga
CA, US
Agent
Kam T Tam
Assignee
MagePower Semiconductor
CA, US
IPC
H01L 21/336
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