06049867 is referenced by 55 patents and cites 24 patents.

A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.

Title
Method and system for multi-thread switching only when a cache miss occurs at a second or higher level
Application Number
473692
Publication Number
6049867
Application Date
August 4, 1997
Publication Date
April 11, 2000
Inventor
James Allen Rose
Rochester
MN, US
Timothy John Mullins
Rochester
MN, US
Steven Raymond Kunkel
Rochester
MN, US
Harold F Kossman
Rochester
MN, US
Ross Evan Johnson
Rochester
MN, US
Richard James Eickemeyer
Rochester
MN, US
Agent
Felsman Bradley Vaden Gunter & Dillon
Agent
Andrew J Dillon
Jack V Musgrove
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/38
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