06035374 is referenced by 109 patents and cites 6 patents.

A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

Title
Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
Application Number
8/881239
Publication Number
6035374
Application Date
June 25, 1997
Publication Date
March 7, 2000
Inventor
Joseph I Chamdani
Santa Clara
CA, US
Ramesh Panwar
Santa Clara
CA, US
Agent
Stuart T Hogan & Hartson Langley
William J Kubida
Assignee
Sun Microsystems
CA, US
IPC
G06F 9/30
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