A multi-phase clock generator is implemented by a delay circuit that receives an input clock signal. The clock generator couples the input clock signal to a first clock output terminal and to a delay circuit. The delay circuit delays the input clock signal to produce a delayed clock signal, and the delayed clock signal is coupled to a second clock output terminal. The first and second clock signals coupled to the first and second clock output terminals are applied to a logic circuit that generates two clock signals and their compliments. These clock signals are used to clock a shift register on both the rising and falling edge of the input clock signal. The shift register may be used in a command buffer for a packetized DRAM, and one or more of the resulting packetized DRAMs may be used in a computer system.