06026050 is referenced by 175 patents and cites 139 patents.

A system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets of the memory device that are captured in a shift register responsive to a transition of the internal clock signal. However, the phase of the internal clock signal is sequentially incremented after each initialization packet has been captured in the shift register. After a plurality of initialization packets have been captured, an evaluation circuit identifies which phases of the internal clock signal clocked the shift register at the proper time to accurately capture each initialization packet. A single phase of the internal clock signal is then selected from within the range of internal clock signal phases that successfully captured initialization packets. This selected phase of the internal clock signal is used during normal operation of the memory device.

Title
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
Application Number
890055
Publication Number
6026050
Application Date
February 10, 1999
Publication Date
February 15, 2000
Inventor
Troy A Manning
Meridian
ID, US
Russel Jacob Baker
Meridian
ID, US
Agent
Dorsey & Whitney
Assignee
Micron Technology
ID, US
IPC
G11C 7/00
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