06021564 is referenced by 153 patents and cites 67 patents.

A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Title
Method for reducing via inductance in an electronic assembly and article
Application Number
746442
Publication Number
6021564
Application Date
September 23, 1998
Publication Date
February 8, 2000
Inventor
David A Hanson
Altoona
WI, US
Agent
Victor M Genco Jr
Assignee
W L Gore & Associates
DE, US
IPC
H01K 3/10
View Original Source