06020760 is referenced by 105 patents and cites 46 patents.

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

Title
I/O buffer circuit with pin multiplexing
Application Number
8/895470
Publication Number
6020760
Application Date
July 16, 1997
Publication Date
February 1, 2000
Inventor
Rakesh H Patel
Cupertino
CA, US
Kevin A Norman
Belmont
CA, US
Michael R Butts
Portland
OR, US
Stephen P Sample
Saratoga
CA, US
Agent
Lyon & Lyon
Assignee
Quickturn Design Systems
CA, US
Altera Corporation
CA, US
IPC
H03K 19/177
H03K 19/173
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