06018304 is referenced by 131 patents and cites 11 patents.

Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.

Title
Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability
Application Number
9/46347
Publication Number
6018304
Application Date
March 23, 1998
Publication Date
January 25, 2000
Inventor
Anthony Bessios
Dallas
TX, US
Agent
Richard L Donaldson
Bret J Petersen
Assignee
Texas Instruments Incorporated
TX, US
IPC
H03M 5/00
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