06016282 is referenced by 258 patents and cites 137 patents.

A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and command busses. Each memory module includes the vernier clock adjustment circuitry.

Title
Clock vernier adjustment
Application Number
9/86401
Publication Number
6016282
Application Date
May 28, 1998
Publication Date
January 18, 2000
Inventor
Brent Keeth
Boise
ID, US
Agent
Seed and Berry
Assignee
Micron Technology
ID, US
IPC
G11C 13/00
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