06013948 is referenced by 342 patents and cites 29 patents.

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.

Title
Stackable chip scale semiconductor package with mating contacts on opposed surfaces
Application Number
563191
Publication Number
6013948
Application Date
April 1, 1998
Publication Date
January 11, 2000
Inventor
Warren M Farnworth
Nampa
ID, US
Alan G Wood
Boise
ID, US
Salman Akram
Boise
ID, US
Agent
Stephen A Gratton
Assignee
Micron Technology
ID, US
IPC
H05K 1/18
H01L 23/36
H01L 23/12
H01L 23/50
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