06011732 is referenced by 186 patents and cites 137 patents.

A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the plurality of signals for producing at least one clock signal in response to control signals input to the plurality of multiplexers. A clock driver is provided for driving the clock signal. A variable delay circuit is positioned to delay the external clock signal before input to the delay-locked loop. A compound feedback loop is responsive to certain of the plurality of signals for producing a control signal input to the variable delay circuit.

Title
Synchronous clock generator including a compound delay-locked loop
Application Number
8/915185
Publication Number
6011732
Application Date
August 20, 1997
Publication Date
January 4, 2000
Inventor
Brent Keeth
Boise
ID, US
Ronnie M Harrison
Boise
ID, US
Agent
Seed and Berry
Assignee
Micron Technology
ID, US
IPC
G11C 7/00
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