06000006 is referenced by 549 patents and cites 38 patents.

A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block. Wear-leveling is performed on a block being written when both total and incremental counts exceed system-wide total and incremental thresholds. The incremental-write count is cleared after a block is wear-leveled, but the total-write count is never cleared. The incremental-write count prevents moving a block again immediately after wear-leveling. The thresholds are adjusted as the system ages to provide even wear.

Title
Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
Application Number
8/918203
Publication Number
6000006
Application Date
August 25, 1997
Publication Date
December 7, 1999
Inventor
Allan J Christie
Fremont
CA, US
Earl T Cohen
Fremont
CA, US
Rolando H Bruce
South San Francisco
CA, US
Ricardo H Bruce
Union City
CA, US
Agent
Stuart T Auvinen
Assignee
BIT Microsystems
CA, US
IPC
G06F 12/10
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