05976912 is referenced by 297 patents and cites 13 patents.

A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Title
Fabrication process of semiconductor package and semiconductor package
Application Number
8/716362
Publication Number
5976912
Application Date
September 18, 1996
Publication Date
November 2, 1999
Inventor
Hiroshi Nomura
Oyama
JP
Noriyuki Taguchi
Tsukuba
JP
Shinsuke Hagiwara
Shimodate
JP
Hirohito Ohhata
Tsukuba
JP
Toshio Yamazaki
Tsukuba
JP
Fumio Inoue
Tsukuba
JP
Yoshiaki Tsubomatsu
Tsuchiura
JP
Naoki Fukutomi
Yuki
JP
Agent
Pennie & Edmonds
Assignee
Hitachi Chemical Company
JP
IPC
H01L 23/28
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