A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to interface between the embedded processor and the reconfigurable portions of the chip, thus allowing for the fastest interface between standard processor code and configurable "hard-wired" functions. A configuration memory stack is provided, allowing for nearly instantaneous reconfiguration. if desired, configuration planes can be shared between ALU function configuration and bus interconnect configuration, allowing more efficient use of stack memory.