05961629 is referenced by 70 patents and cites 63 patents.

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Title
High performance, superscalar-based computer system with out-of-order instruction execution
Application Number
727006
Publication Number
5961629
Application Date
September 10, 1998
Publication Date
October 5, 1999
Inventor
Quang H Trang
San Jose
CA, US
Sze Shun Wang
San Diego
CA, US
Te Li Lau
Palo Alto
CA, US
Johannes Wang
Redwood City
CA, US
Yasuaki Hagiwara
Santa Clara
CA, US
Sanjiv Garg
Freemont
CA, US
Yoshiyuki Miyayama
Santa Clara
CA, US
Derek J Lentz
Los Gatos
CA, US
Le Trong Nguyen
Monte Sereno
CA, US
Agent
Sterne Kessler Goldstein & Fox P L L C
Assignee
Seiko Epson Corporation
JP
IPC
G06F 9/28
G06F 9/38
G06F 9/30
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