05959993 is referenced by 26 patents and cites 32 patents.

A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.

Title
Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture
Application Number
8/714005
Publication Number
5959993
Application Date
September 13, 1996
Publication Date
September 28, 1999
Inventor
Thomas Daniel
Los Altos Hills
CA, US
Subir Varma
San Jose
CA, US
Agent
Oppenheimer Wolff & Donnelly
Assignee
LSI Logic Corporation
CA, US
IPC
H04J 3/00
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