05948098 is referenced by 14 patents and cites 13 patents.

A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction type as performance critical arithmetic instructions and non-performance critical arithmetic instructions. The execution unit comprises a performance critical pipeline to execute the performance critical arithmetic instructions. The execution unit also comprises a non-performance critical pipeline to execute the non-performance critical arithmetic instructions.

Title
Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
Application Number
8/885622
Publication Number
5948098
Application Date
June 30, 1997
Publication Date
September 7, 1999
Inventor
Gary R Lauterbach
Los Altos
CA, US
Arthur T Leung
Sunnyvale
CA, US
Agent
Pennie & Edmonds
Assignee
Sun Microsystems
CA, US
IPC
G06F 9/00
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