05939749 is referenced by 30 patents and cites 9 patents.

A split gate transistor having a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate. A channel region is formed between the source region and the drain region. A floating gate electrode is formed substantially above the channel region. The floating gate electrode has an end surface. A control gate electrode is provided over the semiconductor substrate so as to overlap the floating gate electrode. The control gate electrode has an end surface formed level with the end surface of the floating gate electrode.

Title
Split gate transistor array
Application Number
8/824213
Publication Number
5939749
Application Date
March 25, 1997
Publication Date
August 17, 1999
Inventor
Takayuki Kaida
Gifu-ken
JP
Kaoru Taketa
Ogaki
JP
Agent
Sheridan Ross P C
Assignee
Sanyo Electric Company
JP
IPC
H01L 29/78
H01L 29/68
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