05933023 is referenced by 187 patents and cites 14 patents.

A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to access portions of RAM. In one embodiment, dedicated address and data lines access the RAM blocks of the present invention and are connectable to routing lines in the interconnect structure. These lines allow RAM blocks and arrays of RAM blocks to be configured long, wide, or in between, and allow logic blocks to conveniently access RAM blocks in a remote part of the chip. Access to the RAM blocks is efficient in any RAM configuration. Bidirectional buffers or pass devices segment the address and data lines at each RAM block so that a selectable number of RAM blocks can operate together as a RAM. In another embodiment, dedicated data lines are programmably connectable in a staggered arrangement so that RAM blocks can be connected over a long distance without conflict between the RAM blocks.

Title
FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
Application Number
8/708247
Publication Number
5933023
Application Date
September 3, 1996
Publication Date
August 3, 1999
Inventor
Steven P Young
San Jose
CA, US
Agent
Lois D Cartier
Edel M Young
Assignee
Xilinx
CA, US
IPC
H03K 19/177
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