05924119 is referenced by 78 patents and cites 6 patents.

A shared memory multiprocessor having a packet switched bus for transferring data between a plurality processors, I/O devices, cache memories and main memory employs a bus protocol which permits multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.

Title
Consistent packet switched memory bus for shared memory multiprocessors
Application Number
620508
Publication Number
5924119
Application Date
January 27, 1994
Publication Date
July 13, 1999
Inventor
Jean A Gastinel
Mountain View
CA, US
Jean Marc Frailong
Palo Alto
CA, US
Pradeep S Sindhu
Mountain View
CA, US
Assignee
Xerox Corporation
CT, US
IPC
G06F 12/00
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