05914616 is referenced by 330 patents and cites 33 patents.

The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

Title
FPGA repeatable interconnect structure with hierarchical interconnect lines
Application Number
8/806997
Publication Number
5914616
Application Date
February 26, 1997
Publication Date
June 22, 1999
Inventor
Trevor J Bauer
Campbell
CA, US
Kamal Chaudhary
Milpitas
CA, US
Steven P Young
San Jose
CA, US
Agent
Edel M Young
Lois D Cartier
Assignee
XILINX
CA, US
IPC
H03K 19/177
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