05913111 is referenced by 43 patents and cites 17 patents.

This invention provides a transistor manufacture method comprising the steps of forming, on a semiconductor substrate, an insulating film being made open at least in an introducing portion through which an impurity for forming a drain region other than a lightly-doped region is introduced, then forming a gate electrode and a drain electrode each containing an impurity, and then introducing the impurity through between the gate electrode and the drain electrode to thereby form the lightly-doped region; and introducing the impurity from the drain electrode through the impurity introducing portion with heat treatment, to thereby form the drain region. A transistor manufactured by the above method is also provided.

Title
Method of manufacturing an insulaed gate transistor
Application Number
8/587661
Publication Number
5913111
Application Date
January 17, 1996
Publication Date
June 15, 1999
Inventor
Shunsuke Inoue
Yokohama
JP
Yuzo Kataoka
Hiratsuka
JP
Agent
Fitpatrick Cella Harper & Scinto
Assignee
Canon Kabushiki Kaisha
JP
IPC
H01L 21/38
H01L 21/22
H01L 21/84
H01L 21/00
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