05911052 is referenced by 47 patents and cites 12 patents.

A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

Title
Split transaction snooping bus protocol
Application Number
8/673967
Publication Number
5911052
Application Date
July 1, 1996
Publication Date
June 8, 1999
Inventor
Nalini Agarwal
Sunnyvale
CA, US
Erik Hagersten
Palo Alto
CA, US
Gerald Cheung
Sunnyvale
CA, US
David Broniarczyk
Mountain View
CA, US
Frederick M Cerauskis
Mountain View
CA, US
Jeff Price
Mountain View
CA, US
Bjorn Liencres
Palo Alto
CA, US
Ashok Singhal
Redwood City
CA, US
Agent
Flehr Hohbach Test Albritton & Herbert
Assignee
Sun Microsystems
CA, US
IPC
G06F 13/00
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