05909559 is referenced by 311 patents and cites 22 patents.

An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230). The bus bridge (2236), the bus interface (2220) and the first terminals and the DRAM memory controller (2250) have datapaths selectively interconnected in response to the arbiter circuit (2230). Other devices, systems and methods are also disclosed.

Title
Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width
Application Number
8/832892
Publication Number
5909559
Application Date
April 4, 1997
Publication Date
June 1, 1999
Inventor
John Ling Wing So
Plano
TX, US
Agent
Richard L Donaldson
Gerald E Laws
Robert D Marshall Jr
Assignee
Texas Instruments Incorporated
TX, US
IPC
G06F 13/00
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