05905876 is referenced by 93 patents and cites 13 patents.

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

Title
Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
Application Number
8/766954
Publication Number
5905876
Application Date
December 16, 1996
Publication Date
May 18, 1999
Inventor
D Michael Bell
Beaverton
OR, US
Peter D MacWilliams
Aloha
OR, US
Stephen S Pawlowski
Beaverton
OR, US
Agent
Kenyon & Kenyon
Assignee
Intel Corporation
CA, US
IPC
G06F
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